Using FOR loop in VHDL with a variable

Using FOR loop in VHDL with a variable

Is there any possible way to create a for loop in the form:
for i in 0 to some_var loop
// blah,blah
end loop;
If not, is there any alternative way to create the same loop? Since While
loops allows to use variable as the limit, but they are not synthesizeable
in my project.
Thanks in Advance,
Bojan Matovski